Digital System Test And Testable Design: Using ... -

This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon .

The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage Digital System Test and Testable Design: Using ...

The text treats testing and testability as integral parts of the digital design process rather than afterthoughts. This book is widely used as a primary

Gate-level faults, fault collapsing, and structural modeling in Verilog. Key Technical Coverage The text treats testing and

It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms.

The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered

The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology